The escalating demands for high density and performance associated with non-volatile memory devices, such as electrically erasable programmable read only memory (EEPROM) devices, require small design features, high reliability and increased manufacturing throughput. The reduction of design features, however, challenges the limitations of conventional methodology.
One particular problem with non-volatile memory devices involves junction leakage. For example, leakage currents caused by carriers at the source and/or drain junctions may be injected into the charge storage element during write or erase operations. The junction leakage currents may make it difficult for the memory device to be efficiently programmed or erased. In addition, the junction leakage may also make it difficult for the memory device to meet the expected data retention requirement and, ultimately, may lead to device failure.